1. Field of the Invention
The invention relates to a semiconductor process, and more particularly to a source/drain (S/D) device fabricated process used in a high voltage circuit element.
2. Description of the Related Art
FIGS. 1a to 1i are cross-sections of the conventional method for fabricating S/D device.
In FIG. 1a, a semiconductor substrate 101, such as silicon, is provided, and a first isolating area 105a and a second isolating area 105b are formed thereon. A pad layer 102, such as oxide, a conductive layer 103, such as poly, and a first patterned photo resist layer 104 are sequentially formed in the area between the first isolating area 105a and the second isolating area 105b. The area surrounding the isolating area areas is an active area (AA).
In FIG. 1b, after the conductive layer 103 is etched using the first patterned photo resist layer 104 as a mask to form a gate 103a, the first patterned photo resist layer 104 is removed. Then, the area of the semiconductor substrate 101 between the gate 103a and the first isolating area 105a is doped to form a lightly doped area 106.
In FIG. 1c, an isolating layer 107, such as nitride, is conformably formed on the surface of the pad layer 102 and the gate 103a. 
In FIG. 1d, the isolating layer 107 is isotropically etched to form a spacer 107a on the sidewall of the gate 103a. 
In FIG. 1e, a second patterned photo resist layer 108 having a first opening 109a and a second opening 109b is formed on the semiconductor substrate 110. The first opening 109a is positioned in the area between the gate 103a and the first isolating area 105a, and the second opening 109b is positioned in the area between the gate 103a and the second isolating area 105b. 
First ion implantation is performed on the semiconductor substrate 101 using the second patterned photo resist layer 108 as a mask with As or B ions.
FIG. 2 is a top view of FIG. 1e. In FIG. 2, part of the active area and half the width of the gate 103a are exposed by the first opening 109a in the second patterned photo resist layer 108.
In FIG. 1f, a first doped area 110a is formed at the bottom of the first opening 109a and a second doped area 110b is formed at the bottom of the second opening 109b. After the first ion implantation, the second patterned photo resist layer 108 is removed.
In FIG. 1g, a third patterned photo resist layer 111 having a third opening 112 is formed on the semiconductor substrate 101, and half the width of the gate 103a is exposed by the third opening 112 in the third patterned photo resist layer 111. The third opening 112 is positioned in the area between the gate 103a and the second isolating area 105b. 
Second ion implantation is performed on the semiconductor substrate 101 using the third patterned photo resist layer 111 as a mask and the semiconductor substrate 101 is annealed with As or B ions.
FIG. 3 is a top view of FIG. 1f. In FIG. 3, part of the active area and half the width of the gate 103a are exposed by the first opening 112 in the third patterned photo resist layer 111, and the area between the gate 103a and the first isolating 105a is covered with the third patterned photo resist layer 111.
In FIG. 1h, a deeply doped area 113 is formed at the bottom of the third opening 112. After the second ion implantation, the third patterned photo resist layer 111 is removed. The deeply doped area 113 is 6-7 times the depth of the first doped area 110a and the second doped area lob. The deeply doped area 113 expands after annealing, such that the depth and the width of the deeply doped area 113 are both increased. When the deeply doped area 113 increases, the concentration of dopant inside the deeply doped area 113 decreases and the breakdown voltage of the deeply doped area 113 increases accordingly.
By varying the energy of the ions to form the deeply doped area 113 in the semiconductor substrate 101, implantation depth into the substrate can be controlled. Meanwhile, the ions also penetrate the gate 103a and the spacer 107a into the semiconductor substrate 101, and the size increases after annealing.
The channel between the S/D consisting of the first doped area 110a and another S/D consisting of the second doped area 110b and deeply doped area 113 is decreased, resulting in Short Channel Effect. When the two S/D devices are both deeply doped areas, the channel between the S/D devices below the gate 103a and spacer 107a punches through, such that electrons are injected into the channel from source region before applying a gate voltage.
The present invention is directed to a method for fabricating source/drain devices in a high voltage circuit element without additional process.
Accordingly, the present invention provides a method for fabricating a source/drain device, in which, first, a semiconductor substrate having a gate is provided. A first doped area is positioned on a first side of the gate on the semiconductor substrate, and a second doped area is positioned on a second side of the gate on the semiconductor substrate with spaces between. A patterned photo resist layer having an opening on the second side of the gate is formed on the semiconductor substrate, and the exposed gate is less than half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer as a mask.
Accordingly, the present invention also provides a method for fabricating source/drain devices. A silicon substrate having a gate is provided. A first doped area is positioned on a first side of the gate on the silicon substrate, and a second doped area is positioned on a second side of the gate on the silicon substrate with spaces between. A patterned photo resist layer having an opening on the second side of the gate is formed on the semiconductor substrate, and the width of the exposed gate is 2 xcexcm. The silicon substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer as a mask.
Accordingly, the present invention also provides a method for fabricating a source/drain device. A semiconductor substrate having a pad layer, a gate, a first isolating area and a second isolating area, is provided. The first isolating area is positioned on a first side of the gate and the second isolating area is positioned on a second side of the gate. The gate has a spacer on the sidewall of the gate. A first patterned photo resist layer is formed as a mask to implant into the semiconductor substrate to form a first doped area and a second doped area. The first doped area is positioned between the gate and the first isolating area, and the second doped area is positioned between the gate and second isolating area. A second patterned photo resist layer having an opening on the second side between the gate and the second isolating area is formed on the semiconductor substrate. The exposed gate is less than half the width of the gate. The semiconductor substrate is implanted and annealed using the patterned photo resist layer as a mask to form a dual diffusion area on the second side of the gate. The second patterned photo resist layer is removed.
Accordingly, the present invention also provides a method for fabricating a source/drain device. A silicon substrate having a pad oxide layer, a gate, a first isolating area positioned on a first side of the gate and a second isolating area positioned on a second side of the gate is provided. The gate has a spacer on the sidewall of the gate. A first patterned photo resist layer is formed as a mask to implant the silicon substrate to form a first doped area and a second doped area. The first doped area is positioned between the gate and the first isolating area, and the second doped area is positioned between the gate and second isolating area. The first patterned photo resist layer is removed. A second patterned photo resist layer having an opening on the second side between the gate and the second isolating area is formed on the silicon substrate. The width of the exposed gate is 2 xcexcm. The silicon substrate is implanted and annealed using the patterned photo resist layer as a mask to form a dual diffusion area on the second side of the gate. The second patterned photo resist layer is removed.